As a conventional method which is low in drive voltage to suppress off-leaks and still aimed at obtaining high drive current in CMOS (Complementary Metal Oxide Semiconductor) circuits using MOSFETs, there has been a method in which the well bias voltage is changed between standby and active states (see Japanese Patent Laid-Open Publications HEI 6-216346 and 10-340998).
FIG. 16 shows a schematic cross-sectional view of a MOSFET in which the well bias is changed (hereinafter, the transistor will be referred to as substrate-bias variable transistor). Referring to FIG. 16, there are shown, with reference numerals having the following denotations, a substrate 211, a P-type well region 212, an N-type well region 213, a device isolation region 214, an N-type source region 215, an N-type drain region 216, a P-type source region 217, a P-type drain region 218, a gate insulator 219, a gate electrode 220, a P+ diffusion layer 221 for providing contact with a P-type shallow well region, an N+ diffusion layer 222 for providing contact with an N-type shallow well region, an N-type substrate-bias variable transistor 223, a P-type substrate-bias variable transistor 224, and further numeral 230 denotes a bias generation circuit A and numeral 231 denotes a bias generation circuit B.
The principle of operation of the N-type substrate-bias variable transistor 223 is explained below. It is noted that the P-type substrate-bias variable transistor 224, when reversed in polarity, operates in a similar manner. Referring to the N-type substrate-bias variable transistor 223, when the circuit is in an active state, the a 0 V or positive voltage (with a source voltage referenced) is applied from the bias generation circuit A to the P-type well region. With a positive voltage applied to the P-type well region, the effective threshold lowers due to a substrate-bias effect, and the drive current increases as compared with the case of normal MOSFETs. When the circuit is in a standby state, on the other hand, a negative voltage is applied from the bias generation circuit A to the P-type well region. As a result of this, the effective threshold increases due to the substrate-bias effect, and the off-leak decreases as compared with normal MOSFETs.
As a conventional method which is low in drive voltage and still aimed at obtaining high drive current in CMOS circuits using MOSFETs, there have been dynamic threshold transistors (hereinafter, referred to as DTMOS′). In a DTMOS, the gate electrode and the well region are short-circuited, and the effective threshold lowers only while the device is in the ON state. This makes it possible to increase the drive current alone while the off-leak is maintained as it is. There is disclosed a technique that the above-mentioned substrate-bias variable transistor and the DTMOS are combined together to exploit their respective advantages (Japanese Patent Laid-Open Publication HEI 10-340998).
FIG. 17 shows a cross-sectional view of a device fabricated by this technique. Referring to FIG. 17, there are shown, with reference numerals having the following denotations, a P-type semiconductor substrate 311, an N-type deep well region 312, a P-type deep well region 313, an N-type shallow well region 314, a P-type shallow well region 315, a device isolation region 316, an N-type MOSFET source region 317, an N-type MOSFET drain region 318, a P-type MOSFET source region 319, a P-type MOSFET drain region 320, an N+ diffusion layer 321 for providing contact with an N-type shallow well region, a P+diffusion layer 322 for providing contact with a P-type shallow well region, a gate insulator 323, a gate electrode 324, a P-type substrate-bias variable transistor 325, an N-type substrate-bias variable transistor 326, an N-type DTMOS 327, a P-type DTMOS 328, a well bias input 329 for the P-type substrate-bias variable transistor 325, a well bias input 330 for the N-type substrate-bias variable transistor 326, and a fixed bias input 331 for the P-type deep well. In addition, although not shown, the gate electrode 324 and the P-type shallow well region 315 are electrically short-circuited in the DTMOS 327, and the gate electrode 324 and the N-type shallow well region 314 are electrically short-circuited in the DTMOS 328.
In the DTMOS′ 327 and 328, the voltages of the shallow well regions 315 and 314 change in response to the voltage of the gate electrode 324. Therefore, under each shallow well region is formed a deep well region of opposite polarity, and the recess-type isolation region 316 is formed at enough depth to electrically isolate shallow well regions of its mutually neighboring devices, thereby being electrically isolated from the shallow wells of the neighboring devices. Meanwhile, shallow well regions of substrate-bias variable transistors present in one circuit block have to be provided in common. Therefore, under the P-type shallow well region 315 of the N-type substrate-bias variable transistor 326 in FIG. 17, is formed the P-type deep well region 313, which is integrated with a P-type shallow well region to form a common well region. To this P-type common well region, a voltage that differs between active and standby states is given via the well bias input 330 for the N-type substrate-bias variable transistor 326. In order to prevent any effects on devices of other circuit blocks or the DTMOS portion, the N-type deep well region 312 is formed further deeper in the substrate, by which the P-type deep well region 313 is electrically isolated. Under the shallow well region 314 of the P-type substrate-bias variable transistor 325 in FIG. 17, is formed the N-type deep well region 312, which is integrated with the N-type shallow well region to form a common well region. To this N-type common well region, a voltage that differs between active and standby states is given via the well bias input 329 for the P-type substrate-bias variable transistor. Thus, a circuit in which a substrate-bias variable transistor and a DTMOS are formed on one substrate to exploit their respective advantages can be implemented.
In the circuit using the substrate-bias variable transistors 223 and 224, biases of the well regions 212 and 213 are changed against a plurality of MOSFETs 223 and 224. Accordingly, the MOSFETs 223 or 224 have to share a well region. For this purpose, the depth of the bottom face of the device isolation region 214 in FIG. 16 is set deeper than the depth of the junction between the source regions and drain regions of the MOSFETs 223, 224 and their well region and, at the same time, shallower than the depth of the lower end of the well region.
However, for example, if the conductive type of the semiconductor substrate 211 in FIG. 16 is P type, the P-type well region would be all in common. That is, N-type transistors on the same substrate would be put all into the active state or all into the standby state, as an issue.
In the prior art technique in which the DTMOS and the substrate-bias variable transistor are combined together (Japanese Patent Laid-Open Publication HEI 10-340998), a three-layer well structure (N-type shallow well region 314/P-type deep well region 313/N-type deep well region 312) is formed at the portion of the P-type DTMOS 328 in order to make up the complementary type structure. As a result, the well region would extend to a very large depth. Forming a well having such a very large depth would indispensably involve injection of very high energy, leading to an increase in crystal defect as a result. This in turn would incur an increase in leak current due to the crystal defects. Further, high-temperature annealing for recovering from the crystal defects would be involved, which would cause the diffusion distance of dopants to elongate noticeably. As a result, margin for the boundary of the well regions would increase, which would obstruct the implementation of higher integration.